1. Field of the Invention
This invention relates generally to the structure and fabrication process of gallium arsenide (GaAs) integrated circuits (ICs). More particularly, this invention relates to the structure and fabrication process of GaAs power metal semiconductor field effect transistor (MESFET) integrated circuits (ICs) which has high breakdown voltage and high drain source current (Ids).
2. Description of the Prior Art
Application of the conventional general purpose GaAs MESFET as a power MESFET has two basic limitations. The first limitation is the low level of breakdown voltage and the second limitation is the low drain to source current. The drain to source breakdown voltage depends heavily on the basic FET structure including the configuration and the relative positioning of the cross section of the channel regions while the gate breakdown voltage is closely related to the carrier concentration of the active layer and the pinch off voltage which in turn is related to the drain saturation current per unit gate width.
Because of the inter-dependencies between these structure parameters, in order to overcome the aforementioned limitations, various types of GaAs FET structures and IC processing methods are investigated. FIG. 1 shows a cross-sectional view of a general purpose MESFET IC 10 wherein three types of MESFET structures 20, 30 and 40 are supported on a semi-insulating GaAs substrate 50. Each of these structures has a source, i.e., 22, 32, 42, a gate, i.e. 24, 34, and 44, and a drain, i.e., 26, 36, and 46. Under these sources and the drains, these three MESFET structures all have highly doped and deep N-plus regions, regions 27, 37 and 47. Between the N-plus regions under the source and drain, i.e., regions 27, 37, and 47, all three structures also have a shallower active channel region, i.e., regions 28, 38, and 48, which extends partially into these deeper N-plus regions, i.e., regions 27, 37, and 47.
The only difference between these three structures 20, 30 and 40, are the dopant concentrations of the shallower active channels as represented by regions 28, 38, and 48. In the first structure 20, the region 28 is a depletion and enhancement channel, in the second structure 30, the region 38 is an enhancement channel, and in the third structure 40, the region 48 is a depletion channel. As disclosed by TriQuint in `TQS GaAs QED/A Design Manual` Version 3.0 Rev. -, October. 1991, the relative quantity of the breakdown voltages and drain-source currents are shown in Table 1 below:
TABLE 1 ______________________________________ Breakdown Structure Implantation Voltage Ids ______________________________________ E-FET Enhancement Implantation High Low D-FET Depletion Implantation High Medium M-FET Enhancement and Depletion Low High ______________________________________
These FET structures illustrate that when the active channel under the gate, i.e., regions 28,38, and 48, have lower concentration of dopant, i.e., the E-FET and D-FET types of structures, there is a higher breakdown voltage. However, the lower concentration of dopant in these type of structures also causes the source-drain current to decrease. There seems to have a conflict between these two design parameters with these conventional types of structures that the breakdown voltage and the source to drain current can not be increased simultaneously.
Codella et al. disclose in U.S. Pat. No. 4,632,822 a self aligned GaAs, lightly doped drain MESFET wherein a shallow N-minus (N-) active channel region formed on a GaAs substrate, a Schottky gate overlaying the N- region and highly doped and deep N+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to sub micron levels. In another embodiment, Codella et al. also disclose a structure where a deep p-type pockets are formed under the source/drain extensions to better control the device threshold voltage and to further reduce the channel.
The GaAs MESFET self-aligned structure as disclosed by Codella is able to reduce the series resistance and shorten the channel length by the use lightly doped source/drain extensions which diminishes the short channel effects by preventing the drain electric field to extend into the active channel underneath the gate. However, for the purpose of providing a power MESFET, the dopant concentration of the lightly doped region in the gate extension areas is too low to generate a high drain-source current as required by the power GaAs MESFET.
F. Hasegawa discloses in `GaAs FET Principle and Technology` (Artech House 1982), that the breakdown voltage can be increased by a FET structure where the active channel region is recessed. FIG. 2 represents such an structure where a cross sectional view of the proposed FET structure 70 is shown. The IC structure is built on a semi-insulating GaAs substrate 75 with an overlaying buffer 80. There is a source 85, a gate 90, and a drain 95 on top of an active channel region 97. There is a gradual recess 99 of the active channel region 97 near the gate 95. This is structure according to Hasegawa will increase the drain breakdown voltage. However, such structure has only limited applications and is not suitable for use in low noise power amplifier which does not provide a solution to overcome the difficulty in implementing GaAs ICs in power MESFET circuits.
Therefore, there is still a need in the art of GaAs power MESFET design and manufacture to provide a structure and fabrication process that would resolve these limitations.